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preliminary 2.5v 4k/16k/64k x 80 unidirectional synchronous fifo with bus matching cy7c4808v25 cy7c4806v25 CY7C4804V25 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06028 rev. *b revised december 26, 2002 sure c025/0251 features ? high-speed, low-power, unidirectional, first-in first-out (fifo) memories with bus-matching capabilities 64k 80 (cy7c4808v25) 16k 80 (cy7c4806v25) 4k 80 (CY7C4804V25) 2.5v 100 mv power supply all i/os are 1.5v hstl individual clock frequency up to 200 mhz (5-ns read/write cycle times) high-speed access with t a = 3.8 ns bus matching on both ports: 80, 40, 20, 10 free-running clka and clkb. clocks may be asyn- chronous or coincident cypress standard or first-word fall-through modes serial and parallel programming of almost empty/full flags, each with three default values (8, 16, 64) master and partial reset capability retransmit capability big or little endian format 288 fbga 19 mm 19 mm (1.0-mm ball pitch) packaging width and depth expansion capability fabricated using cypress 0.21-micron cmos technol- ogy for optimum speed/power preliminary top-level block diagram port a control logic port b control logic bus matching input register bus matching output register dual-ported status flag logic programmable flag 4k/16k/64k 80 fifo clka csa ena mr pr ff /ir af fs0/sd fs1/sen a 79 ? 0 b 79 ? 0 clkb csb enb be/fwft size1b size2b ef /or ae read data path logic 80 80 reset logic size1a size2a write data path logic rt /spm jtag controller tdi tck tms trst tdo oe read pointer pointer write offset registers memory array
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 2 of 30 pin configuration for CY7C4804V25 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 av ddq v ddq a16 a19 v ddq a30 a34 gnd clka a42 gnd a48 a51 v ddq a55 a57 v ddq v ddq a bv ddq a10 a14 a17 v ddq a29 a33 gnd a39 a41 gnd a45 a50 v ddq a54 a56 a58 v ddq b ca9 a8 v ddq a13 a18 a28 a32 a36 a38 v ddq a44 a46 a49 a52 a53 v ddq a59 a60 c da7 a6 a11v ddq a20 gnd a27 gnd gnd ff /ir v dd a43 gnd a47 v ddq a63 a67 a69 d ev ddq v ddq mr pr v dd a25 gnd fs1/ sen gnd gnd af gnd gnd v dd tdi a66 v ddq v ddq e fa12a15size 1a gnd a21 a24 a31 a35 a37 ena csa a40 a61 v dd gnd a64 a65 a68 f ga5 a2size 2b fs0/ sd gnd a23 a62 gnd tdo a70 a71 a72 g hgndgnd rt/ spm v dd size 1b a4 a73 a74 tck a75 gnd gnd h jb2 b3v ddq a1 gnd a0 a76 gnd gnd a77 a78 a79 j k b6 b7 b4 gnd gnd a3 b76 gnd b77 v ddq b78 b79 k l gnd gnd b5 be/ fwft a22 a26 b73 b74 tms b75 gnd gnd l m b10 b9 vref b8 gnd size 2a b69 gnd trst b70 b71 b72 m n b14 b13 b12 gnd b1 b11 b31 b35 b37 b40 b43 b45 b65 nc gnd b66 b67 b68 n pv ddq v ddq b15 nc nc b0 gnd ef / or gnd gnd csb gnd nc v dd oe b64 v ddq v ddq p rb18 b17 b16v ddq nc gnd nc v dd ae gnd v dd enb gnd nc v ddq b61 b62 b63 r t b20 b19 v ddq b24 b27 b28 b32 b36 v ddq b41 b44 b46 b49 b52 b53 v ddq b59 b60 t uv ddq b21 b22 b25 v ddq b29 b33 gnd b38 b42 gnd b47 b50 v ddq b54 b56 b58 v ddq u vv ddq v ddq b23 b26 v ddq b30 b34 gnd b39 clkb gnd b48 b51 v ddq b55 b57 v ddq v ddq v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 3 of 30 pin configuration for cy7c4806v25 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 av ddq v ddq a16 a19 v ddq a30 a34 gnd clka a42 gnd a48 a51 v ddq a55 a57 v ddq v ddq a bv ddq a10 a14 a17 v ddq a29 a33 gnd a39 a41 gnd a45 a50 v ddq a54 a56 a58 v ddq b ca9 a8 v ddq a13 a18 a28 a32 a36 a38 v ddq a44 a46 a49 a52 a53 v ddq a59 a60 c da7 a6 a11v ddq a20 gnd a27 gnd gnd ff /ir v dd a43 gnd a47 v ddq a63 a67 a69 d ev ddq v ddq mr pr v dd a25 gnd fs1/ sen gnd gnd af gnd v dd v dd tdi a66 v ddq v ddq e fa12a15size 1a gnd a21 a24 a31 a35 a37 ena csa a40 a61 v dd gnd a64 a65 a68 f ga5 a2size 2b fs0/ sd gnd a23 a62 gnd tdo a70 a71 a72 g hgndgnd rt/ spm v dd size 1b a4 a73 a74 tck a75 gnd gnd h jb2 b3v ddq a1 gnd a0 a76 gnd gnd a77 a78 a79 j k b6 b7 b4 gnd gnd a3 b76 gnd b77 v ddq b78 b79 k lgndgnd b5 be/ fwft a22 a26 b73 b74 tms b75 gnd gnd l m b10 b9 vref b8 gnd size 2a b69 gnd trst b70 b71 b72 m n b14 b13 b12 gnd b1 b11 b31 b35 b37 b40 b43 b45 b65 nc gnd b66 b67 b68 n pv ddq v ddq b15 nc nc b0 gnd ef / or gnd gnd csb gnd nc v dd oe b64 v ddq v ddq p rb18 b17 b16v ddq nc gnd nc v dd ae gnd v dd enb gnd nc v ddq b61 b62 b63 r tb20 b19 v ddq b24 b27 b28 b32 b36 v ddq b41 b44 b46 b49 b52 b53 v ddq b59 b60 t uv ddq b21 b22 b25 v ddq b29 b33 gnd b38 b42 gnd b47 b50 v ddq b54 b56 b58 v ddq u vv ddq v ddq b23 b26 v ddq b30 b34 gnd b39 clkb gnd b48 b51 v ddq b55 b57 v ddq v ddq v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 4 of 30 pin configuration for cy7c4808v25 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 av ddq v ddq a16 a19 v ddq a30 a34 gnd clka a42 gnd a48 a51 v ddq a55 a57 v ddq v ddq a bv ddq a10 a14 a17 v ddq a29 a33 gnd a39 a41 gnd a45 a50 v ddq a54 a56 a58 v ddq b ca9 a8 v ddq a13 a18 a28 a32 a36 a38 v ddq a44 a46 a49 a52 a53 v ddq a59 a60 c da7 a6 a11v ddq a20 gnd a27 gnd gnd ff /ir v dd a43 gnd a47 v ddq a63 a67 a69 d ev ddq v ddq mr pr v dd a25 gnd fs1/ sen gnd gnd af gnd gnd v dd tdi a66 v ddq v ddq e fa12a15size 1a gnd a21 a24 a31 a35 a37 ena csa a40 a61 gnd gnd a64 a65 a68 f ga5 a2size 2b fs0/ sd gnd a23 a62 gnd tdo a70 a71 a72 g hgndgnd rt/ spm v dd size 1b a4 a73 a74 tck a75 gnd gnd h jb2 b3v ddq a1 gnd a0 a76 gnd gnd a77 a78 a79 j k b6 b7 b4 gnd gnd a3 b76 gnd b77 v ddq b78 b79 k l gnd gnd b5 be/ fwft a22 a26 b73 b74 tms b75 gnd gnd l m b10 b9 vref b8 gnd size 2a b69 gnd trst b70 b71 b72 m n b14 b13 b12 gnd b1 b11 b31 b35 b37 b40 b43 b45 b65 nc gnd b66 b67 b68 n pv ddq v ddq b15 nc nc b0 gnd ef / or gnd gnd csb gnd nc v dd oe b64 v ddq v ddq p rb18 b17 b16v ddq nc gnd nc v dd ae gnd v dd enb gnd nc v ddq b61 b62 b63 r t b20 b19 v ddq b24 b27 b28 b32 b36 v ddq b41 b44 b46 b49 b52 b53 v ddq b59 b60 t uv ddq b21 b22 b25 v ddq b29 b33 gnd b38 b42 gnd b47 b50 v ddq b54 b56 b58 v ddq u vv ddq v ddq b23 b26 v ddq b30 b34 gnd b39 clkb gnd b48 b51 v ddq b55 b57 v ddq v ddq v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 5 of 30 functional description the cy7c480xv25 family of fifos is comprised of high-speed, low-power, cmos synchronous (clocked) fifo memories, meaning both independent ports employ a synchronous interface. all data transfers through a port are gated to the low-to-high transition of the clock on either port by the enable signal. the clocks for each port are independent of one another and can be asynchronous or coincident. the enable for each port is arranged to provide a simple unidirec- tional interface between microprocessors and/or buses with synchronous control. two kinds of reset are available on the cy7c480xv25: master reset and partial reset. master reset initializes the read and write pointers to the first location of the memory array, configures the fifo for big endian or little endian byte arrangement, selects the cypress standard or first-word fall-through (fwft) mode, and determines the configuration of the programmable flags. the flags can be programmed either in serial mode or in parallel mode. the fifo also comes with three possible default flag offset settings: 8, 16, or 64. partial reset also sets the read and write pointers to the first location of the memory. unlike master reset, any settings existing prior to partial reset (i.e., programming method and partial flag default offsets) are retained. partial reset is useful since it permits flushing of the fifo memory without changing any configuration settings. the cy7c480xv25 have two modes of operation: cypress standard mode or fwft mode. in the cypress standard mode, the first word written to an empty fifo is deposited into the memory array. a read operation is required to access that word (along with all other subsequent words residing in memory). in the fwft mode, the first word written to an empty fifo appears automatically on the outputs, and no read operation is required. nevertheless, accessing subsequent words does necessitate formal read request. fwft mode is primarily used for cascading multiple fifos. the fifo has an ef /or flag on port b and ff /ir flag on port a. the ef and ff functions are selected in the cypress standard mode. ef indicates whether or not the fifo memory is empty. ff shows whether or not the memory is full. the ir and or functions are selected in the fwft mode. ir indicates whether or not the fifo has memory locations available. or shows whether the fifo has data available for reading or not. it marks the presence of valid data on the outputs. the fifo has a programmable almost empty flag (ae ) and a programmable almost full flag (af ). ae indicates the number of words left in the fifo memory is at the user-defined amount. af indicates the number of words written into the fifo memory has achieved a predetermined amount. ff /ir and af flags are synchronized to port a clock that writes data into its array. ef /or and ae flags are synchronized to port b clock that reads data from its array. programmable offsets for ae and af are loaded in parallel via port a or in serial via the sd input. the serial programming mode (spm ) pin makes this selection. three default offsets setting are also provided. the ae threshold can be set at 8, 16, or 64 locations from the empty boundary and af threshold can be set at 8, 16, or 64 locations from the full boundary. all these choices are made using the fs0 and fs1 inputs during master reset. the cy7c480xv25 fifos are characterized for operation from 0 c to 70 c (commercial) and ? 40 c to 85 c (industrial). selection guide cy7c480xv25-200 cy7c480xv25-166 unit maximum frequency 200 166 mhz maximum access time 3.8 4.0 ns minimum cycle time 5 6 ns minimum data or enable set-up 1.0 1.5 ns minimum data or enable hold 0.6 0.6 ns maximum flag delay 3.8 4.0 ns cy7c4808v25 cy7c4806v25 CY7C4804V25 density 64k 80 16k 80 4k 80 package 288 fbga 288 fbga 288 fbga
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 6 of 30 pin description pin description v ddq power supply for i/os v dd power supply for internal logic gnd ground v ref reference voltage mr master reset pr partial reset a 0 ? a 79 input data bus b 0 ? b 79 output data bus ena port a enable pin enb port b enable pin csa port a chip select csb port b chip select oe output enable clka port a clock clkb port b clock be/fwft big/little endian and cypress standard/fwft mode select pin size1a, size2a port a bus size configuration pins size1b, size2b port b bus size configuration pins rt /spm retransmit pin/serial programming select tdi, tdo, tck, tms, trst jtag pins fs1/sen , fs0/sd programmable flags configuration pins ef /or empty/output ready flag (port b) ff /ir full/input ready flag (port a) ae programmable almost empty flag (port b) af programmable almost full flag (port a)
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 7 of 30 signal description master reset (mr ) the fifo memory of the cy7c480xv25 undergoes a complete reset by taking its associated master reset (mr ) input low for at least four clock edges of the slowest clock. the master reset input can switch asynchronously to the clocks. a master reset initializes the internal read and write pointers and forces the full/input ready flag (ff /ir) low, the empty/output ready flag (ef /or) low, the almost empty flag (ae ) low, and the almost full flag (af ) high. after a master reset, the fifo ? s full/input ready flag is set high after two clock cycles to begin normal operation. a master reset must be performed on the fifo after power up, before data is written to its memory. a low-to-high transition on a fifo master reset (mr ) input latches the value of the big endian (be) input, determining the order by which bytes are transferred through port b. a low-to-high transition on a fifo reset (mr ) input latches the values of the flag select (fs0, fs1) and serial programming mode (spm ) inputs for choosing the almost full and almost empty offset programming method (see almost empty and almost full flag offset programming below). partial reset (pr ) the fifo memory of the cy7c480xv25 undergoes a limited reset by taking its associated partial reset (pr ) input low for at least four clock edges of the slowest clock. the partial reset inputs can switch asynchronously to the clocks. a partial reset initializes the internal read and write pointers and forces the full/input ready flag (ff /ir) low, the empty/output ready flag (ef /or) low, the almost empty flag (ae ) low, and the almost full flag (af ) high. after a partial reset, the fifo ? s full/input ready flag is set high after two clock cycles to begin normal operation. whatever flag offsets, programming method (parallel or serial), and timing mode (fwft or cypress standard mode) are currently selected at the time a partial reset is initiated, those settings will remain unchanged upon completion of the partial reset operation. a partial reset may be useful in the case where reprogramming a fifo following a master reset would be inconvenient. big endian/first-word fall-through (be/fwft ) this is a dual-purpose pin. at the time of master reset, the be select function is active, permitting a choice of big or little endian byte arrangement for data written to or read from either one of the ports. this selection determines the order by which bytes (or short words or words) of data are transferred through this port. for the following examples, assume that a byte (or short words or word) bus size has been selected for port b. (note that when port b is configured for a long-word size, the big endian function has no application and the be input is a ? don ? t care. ? ) a high on the be/fwft input when the master reset (mr ) input goes from low to high will select a big endian arrangement. when data is moving from port a to port b, the most significant byte (short word/word) of the long-word written to port a will be transferred to port b first; the least significant byte (short word/word) of the long-word written to port a will be transferred to port b last. a low on the be/fwft input when the master reset (mr ) input goes from low to high will select a little endian arrangement. when data is moving from port a to port b, the least significant byte (short word/word) of the long-word written to port a will be transferred to port b first; the most significant byte (short word/word) of the long-word written to port a will be transferred to port b last. after master reset, the fwft select function is active, permitting a choice between two possible timing modes: cypress standard mode or fwft mode. once the master reset (mr ) input is high, a high on the be/fwft input at the second low-to-high transition of clka will select cypress standard mode. this mode uses the empty flag function (ef ) to indicate whether or not there are any words present in the fifo memory. it uses the full flag function (ff ) to indicate whether or not the fifo memory has any free space for writing. in cypress standard mode, every word read from the fifo, including the first, must be requested using a formal read operation. once the master reset (mr ) input is high, a low on the be/fwft input at the second low-to-high transition of clka will select fwft mode. this mode uses the output ready function (or) to indicate whether or not there is valid data at the data outputs (b 0 ? 79 ). it also uses the input ready function (ir) to indicate whether or not the fifo memory has any free space for writing. in the fwft mode, the first word written to an empty fifo goes directly to data outputs, no read request necessary. subsequent words must be accessed by performing a formal read operation. following master reset, the level applied to the be/fwft input must remain static throughout the fifo operation. programming the almost empty and almost full flags two registers in the cy7c480xv25 are used to hold the offset values for the almost empty and almost full flags. the port b almost empty flag (ae ) offset register is labeled x. the port a almost full flag (af ) offset register is labeled y. the index of each register name corresponds with preset values during the reset of a fifo, programmed in parallel using the fifo ? s port a data inputs, or programmed in serial using the serial data (sd) input (see table 2 ). to l o a d a f i f o ? s almost empty flag and almost full flag offset registers with one of the three preset values listed in table 2 , the serial program mode (spm ) and at least one of the flag-select inputs must be high during the low-to-high transition of its master reset input (mr ). for example, to load the preset value of 64 into x and y, spm , fs0, and fs1 must be high at the rising edge of the fifo reset (mr ). to program the x and y registers from port a, perform a master reset with spm high and fs0 and fs1 low during the low-to-high transition of mr . after this reset is complete, the first two writes to the fifo do not store data in memory but load the offset registers in the order y and x. the port a data inputs used by the offset registers are (a 0 ? 11 ), (a 0 ? 13 ), or (a 0 ? 15 ),for the cy7c480xv25, respectively. the highest numbered input is used as the most significant bit of the binary number in each case. valid programming values for the registers range from 0 to 4095 for the CY7C4804V25; 0 to 16383 for the cy7c4806v25; 0 to 65535 for the cy7c4808v25. fifos begin normal operation after programming is complete.
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 8 of 30 to program the x and y registers serially, initiate a master reset with spm low, fs0/sd low, and fs1/sen high during the low-to-high transition of mr . after this reset is complete, the x and y register values are loaded bit-wise through the fs0/sd input on each low-to-high transition of clka with the fs1/sen input low. twenty-four, twenty-eight or thirty-two bit writes are needed to complete the programming. the two registers are written in the order y then finally x. the first-bit write stores the most significant bit of the y register and the last-bit write stores the least significant bit of the x register. when the option to program the offset registers serially is chosen, the port a full/input ready (ff /ir) flag remains low until all register bits are written. ff /ir is set high by the second low-to-high transition of clka after the last bit is loaded to allow normal fifo operation. spm , fs0/sd, and fs1/sen function the same way in both cypress standard and fwft modes. fifo write/read operation the state of the port a data (a 0 ? 79 ) lines is controlled by port a chip select (csa ). data is loaded into the fifo from the a 0 ? 79 inputs on a low-to-high transition of clka when csa is low, ena is high, and ff /ir is high (see table 3 ). fifo writes on port a are independent of any concurrent port b operation. the port b control signals are identical to those of port a. the state of the port b data (b 0 ? 79 ) lines is controlled by the port b chip select (csb ) and output enable (oe ). the b 0 ? 79 lines are in the high-impedance state when csb or oe is high. the b 0 ? 79 lines are active outputs when csb and oe are low. data is transferred to the b 0 ? 79 outputs by a low-to-high transition of clkb when csb is low, oe is low, enb is high, and ef /or is high (see table 4 ). fifo reads and writes on port b are independent of any concurrent port a operation. the set-up and hold time constraints to the port clocks for the port chip selects are only for enabling write and read opera- tions and are not related to high-impedance control of the data outputs. if a port enable is low during a clock cycle, the port ? s chip select may change states during the set-up and hold time window of the cycle. when operating the fifo in fwft mode and the output ready flag is low, the next word written is automatically sent to the fifo ? s output register by the low-to-high transition of clkb, data residing in the fifo ? s memory array is clocked to the output register only when a read is selected using the port ? s chip select, and enable. when operating the fifo in cypress standard mode, data residing in the fifo ? s memory array is clocked to the output register only when a read is selected using the port ? s chip select, and enable. synchronized fifo flags each fifo is synchronized to its port clock through at least two flip-flop stages. this is done to improve flag-signal reliability by reducing the probability of the metastable events when clka and clkb operate asynchronously to one another. ef /or and ae are synchronized to clkb. ff /ir and af are synchronized to clka. table 5 shows the relationship of each port flag to the fifo. empty/output ready flags (ef /or) these are dual-purpose flags. in the fwft mode, the output ready (or) function is selected. when the output ready flag is high, new data is present in the fifo output register. when the output ready flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored. in the cypress standard mode, the empty flag (ef ) function is selected. when the empty flag is high, data is available in the fifo ? s memory for reading to the output register. when empty flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored. the empty/output ready flag of a fifo is synchronized to clkb. for both the fwft and cypress standard modes, the fifo read pointer is incremented each time a new word is clocked to its output register. the state machine that controls an output ready flag monitors a write pointer and read pointer comparator that indicates when the fifo status is empty, empty+1, or empty+2. in fwft mode, from the time a word is written to a fifo, it can be shifted to the fifo output register in a minimum of four cycles of clkb. therefore, the clkb output ready flag is low if a word in memory is the next data to be sent to the fifo output register and four cycles have not elapsed since the time the word was written. the output ready flag of the fifo remains low until the fourth low-to-high transition of clkb occurs, simultaneously forcing the output ready flag high and shifting the word to the fifo output register. in the cypress standard mode, from the time a word is written to a fifo, the empty flag will indicate the presence of data available for reading in a minimum of three cycles of clkb. therefore, an empty flag is low if a word in memory is the next data to be sent to the fifo output register and three cycles have not elapsed since the time the word was written. the empty flag of the fifo remains low until the third low-to-high transition of clkb occurs, forcing the empty flag high; only then can data be read. a low-to-high transition on the clkb begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subse- quent clock cycle can be the first synchronization cycle. full/input ready flags (ff /ir) this is a dual-purpose flag. in fwft mode, the input ready (ir) function is selected. in cypress standard mode, the full flag (ff ) function is selected. for both timing modes, when the full/input ready flag is high, a memory location is free in the memory to receive new data. no memory locations are free when the full/input ready flag is low and attempted writes to the fifo are ignored. the full/input ready flag of a fifo is synchronized to clka. for both fwft and cypress standard modes, each time a word is written to a fifo, its write pointer is incremented. the state machine that controls a full/input ready flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is full, full ? 1, or full ? 2. from the time a word is read from a fifo, its previous memory location is ready to be written to in a minimum of two cycles clka. therefore, a full/input ready flag is low if less than two cycles of clka have elapsed since the next memory write location has been read. the second low-to-high transition on clka after the read sets the full/input ready flag high.
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 9 of 30 a low-to-high transition on clka begins the first synchro- nization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clock cycle can be the first synchronization cycle. almost empty flags (ae ) the almost empty flag of a fifo is synchronized to clkb. the state machine that controls an almost empty flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is almost empty, almost empty+1, or almost empty+2. the almost empty state is defined by the contents of register x for ae . these registers are loaded with preset values during a fifo reset, programmed from port a, or programmed serially (see almost empty flag and almost full flag offset programming above). an almost empty flag is low when its fifo contains x or less words and is high when its fifo contains (x + 2) or more words. a low-to-high transition of clkb begins the first synchroni- zation cycle if it occurs at time t skew2 or greater after the write that fills the fifo to (x + 2) words. otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. almost full flags (af ) the almost full flag of a fifo is synchronized to clka. the state machine that controls an almost full flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is almost full, almost full ? 1, or almost full ? 2. the almost full state is defined by the contents of register y for af . these registers are loaded with preset values during a fifo reset, programmed from port a, or programmed serially (see almost empty flag and almost full flag offset programming above). an almost full flag is low when the number of words in its fifo is greater than or equal to (4096 ? y), (16384 ? y), or (65536 ? y), for the cy7c480xv25, respectively. an almost full flag is high when the number of words in its fifo is less than or equal to [4096 ? (y + 2)], [16384 ? (y + 2)], or [65536 ? (y + 2)], for the cy7c480xv25, respectively. a low-to-high transition of clka begins the first synchroni- zation cycle if it occurs at time t skew2 or greater after the read that reduces the number of words in memory to [4096/16384/65536 ? (y + 2)]. otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. bus sizing both port a and port b buses can be configured in an 80-bit long word, 40-bit word, 20-bit short word or 10-bit byte format. the levels applied to bus size select (size1a, size2a, size1b, size2b) determine the bus size. bus size on either port can be set independent of each other. these levels should be static throughout fifo operation. both bus size selections are implemented at the completion of master reset, by the time the full/input ready flag is set high. only 80-bit long word data is written to or read from the two fifo memories. bus-matching operations are done before the data is written into the memory (for port a) and after (for port b) data is read from the memory. bus-matching fifo reads data is read from the fifo memory in 80-bit long-word incre- ments. if a long-word bus size is implemented, the entire long- word immediately shifts to the fifo output register. if byte or word size is implemented on port b, only the first one or two bytes appear on the selected portion of the fifo output register, with the rest of the long-word stored in auxiliary registers. in this case, subsequent fifo reads output the rest of the long-word to the fifo output register. when reading data from the fifo in the byte, short word, or word format, the unused outputs will be low. retransmit (rt ) the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred and at least one word has been read since the last reset cycle. a low pulse on rt resets the internal read pointer to the first physical location of the fifo. clka and clkb may be free running but enb must be deasserted during the retransmit pulse and remain deasserted until after the empty/output ready flag (ef /or) goes high. with every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it arrives at the same location as the write pointer. flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data written to the fifo after activation of rt are transmitted also. the full depth of the fifo can be repeatedly retransmitted.
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 10 of 30 table 1. endian/bus matching configuration [1] each character ( ? a ? , ? b ? ,..., ? h ? ) represents 10-bit data be/fwft size 1a size 2a port a size 1b size 2b port b bit#79 bit#0 1 0 0 x80 0 0 x80 write to fifo abcdefgh read from fifo abcdefgh 0 1 x40 read from fifo abcd efgh 1 0 x20 read from fifo ab cd ef gh 1 1 x10 read from fifo a b c d e f g h 0 1 x40 0 0 x80 write to fifo abcd efgh read from fifo abcdefgh 0 1 x40 read from fifo abcd efgh 1 0 x20 read from fifo ab cd ef gh 1 1 x10 read from fifo a b c d e f g h note: 1. be is selected at master reset; size1a, size2a, size1b, and size2b must be static throughout device operation.
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 11 of 30 1 0 x20 0 0 x80 write to fifo ab cd ef gf read from fifo abcdefgh 0 1 x40 read from fifo abcd efgh 1 0 x20 read from fifo ab cd ef gh 1 1 x10 read from fifo a b c d e f g h table 1. endian/bus matching configuration [1] (continued) each character ( ? a ? , ? b ? ,..., ? h ? ) represents 10-bit data be/fwft size 1a size 2a port a size 1b size 2b port b bit#79 bit#0
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 12 of 30 1 1 1 x10 0 0 x80 write to fifo a b c d e f g h read from fifo abcdefgh 0 1 x40 read from fifo abcd efgh 1 0 x20 read from fifo ab cd ef gh 1 1 x10 read from fifo a b c d e f g h table 1. endian/bus matching configuration [1] (continued) each character ( ? a ? , ? b ? ,..., ? h ? ) represents 10-bit data be/fwft size 1a size 2a port a size 1b size 2b port b bit#79 bit#0
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 13 of 30 0 0 0 x80 0 0 x80 write to fifo abcdefgh read from fifo abcdefgh 0 1 x40 read from fifo efgh abcd 1 0 x20 read from fifo gh ef cd ab 1 1 x10 read from fifo h g f e d c b a 0 1 x40 0 0 x80 write to fifo abcd efgh read from fifo efghabcd 0 1 x40 read from fifo abcd efgh 1 0 x20 read from fifo cd ab gh ef 1 1 x10 read from fifo d c b a h g f e table 1. endian/bus matching configuration [1] (continued) each character ( ? a ? , ? b ? ,..., ? h ? ) represents 10-bit data be/fwft size 1a size 2a port a size 1b size 2b port b bit#79 bit#0
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 14 of 30 0 1 0 x20 0 0 x80 write to fifo ab cd ef gh read from fifo gh ef cd ab 0 1 x40 read from fifo cdab ghef 1 0 x20 read from fifo ab cd ef gh 1 1 x10 read from fifo b a d c f e h g 1 1 x10 0 0 x80 write to fifo a b c d e f g h read from fifo hgfedcba 0 1 x40 read from fifo dcba hgfe 1 0 x20 read from fifo ba dc fe hg table 1. endian/bus matching configuration [1] (continued) each character ( ? a ? , ? b ? ,..., ? h ? ) represents 10-bit data be/fwft size 1a size 2a port a size 1b size 2b port b bit#79 bit#0
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 15 of 30 0 1 1 x10 1 1 x10 read from fifo a b c d e f g h table 1. endian/bus matching configuration [1] (continued) each character ( ? a ? , ? b ? ,..., ? h ? ) represents 10-bit data be/fwft size 1a size 2a port a size 1b size 2b port b bit#79 bit#0 table 2. flag programming spm fs1/sen fs0/sd mr x and y registers [2] h h h 64 h h l 16 h l h 8 h l l parallel programming via port a l h l serial programming via sd l h h reserved l l h reserved l l l reserved table 3. port a enable function csa ena clka a 0 ? 79 inputs port function h x x in high-impedance state none l l x in high-impedance state none lh in high-impedance state fifo write table 4. port b enable function csb enb clkb b 0 ? 79 outputs port function h x x in high-impedance state none l l x active, fifo output register none lh active, fifo output register fifo read note: 2. x register holds the offset for ae ; y register holds the offset for af.
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 16 of 30 table 5. fifo flag operation (cypress standard and fwft modes) number of words in fifo memory [4, 5, 6, 7] synchronized to clkb synchronized to clka CY7C4804V25 cy7c4806v25 cy7c4808v25 ef /or ae af ff /ir 0 0 0 l l h h 1 to x 1 to x 1 to x h l h h (x + 1) to [4096 ? (y + 1)] (x + 1) to [16834 ? (y + 1)] (x + 1) to [65536 ? (y + 1)] h h h h (4096 ? y1) to 4095 (16384 ? y1) to 16383 (65536 ? y1) to 65535 h h l h 4096 16384 65536 h h l l 2.5v 64k 80 unidirectional synchronous fifo w/bus matching [3] speed (mhz) ordering code package name packagetype operating range 166 cy7c4808v25-166bbc bb288 288-ball grid array (1.0-mm pitch, 19 19mm) commercial 200 cy7c4808v25-200bbc 200 cy7c4808v25-200bbi bb288 288-ball grid array (1.0-mm pitch, 19 19mm) industrial 2.5v 16k 80 unidirectional synchronous fifo with bus matching speed (mhz) ordering code package name package type operating range 166 cy7c4806v25-166bbc bb288 288-ball grid array (1.0-mm pitch, 19 19mm) commercial 200 cy7c4806v25-200bbc 2.5v 4k 80 unidirectional synchronous fifo with bus matching speed (mhz) ordering code package name package type operating range 166 CY7C4804V25-166bbc bb288 288-ball grid array (1.0-mm pitch, 19 19mm) commercial 200 CY7C4804V25-200bbc notes: 3. shaded areas contain advance information. 4. x is the almost empty offset for fifo used by ae . y is the almost full offset for fifo used by af . both x and y are selected during a fifo reset or port a programming. 5. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. 6. data in the output register does not count as a ? word in fifo memory. ? since in fwft mode the first word written to an empty fifo goes unrequested to the output register (no read operation necessary), it is not included in the fifo memory count. 7. the or and ir functions are active during fwft mode; the ef and ff functions are active in cypress standard mode.
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 17 of 30 maximum ratings [8] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................... ? 65 c to +150 c ambient temperature with power applied............................................... ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +3.6v dc voltage applied to outputs in high z state [9] .................................. ? 0.5v to v ddq + 0.5v dc input voltage [9] ............................... ? 0.5v to v ddq + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage........................................... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 2.5v 100 mv 1.4v to 1.9v industrial ? 40 c to +85 c dc specifications (all i/os except jtag ports will be at hstl level) [10, 11, 14] parameter description test conditions cy7c480xv25 unit min. max. v dd power supply voltage 2.4 2.6 v v ddq i/o supply voltage 1.4 1.9 v v ref input reference voltage typical value = 0.75v 0.7 1.0 v v oh output high voltage i oh = ? 8ma v ddq ? 0.4 v ddq v v ol output low voltage i ol =8 ma v ss 0.4 v v ih (dc) input high voltage v ref + 0.1 [13] v ddq + 0.3 v v il (dc) input low voltage ? 0.3 v ref ? 0.1 [13] v v oh_jtag jtag port output high volt- age i oh = ? 100 a 2.1 v i oh = ? 2 ma 1.7 v v ol_jtag jtag port output low voltage i ol = 100 a 0.2 v i ol = 2 ma 0.7 v v ih_jtag jtag port input high voltage v out > v voh (min.) 1.7 v dd +0.3 v v il_jtag jtag port input low voltage v out < v vol (max.) ? 0.3 0.7 v i ix input leakagecurrent ? 10 +10 a i ozl ,i ozh output off, high z current ? 10 +10 a i sb average standby current 40 [12] ma i cc operating current (typical) v dd = max., i out = 0 ma 600 480 ma operating current (max.) 680 560 ma notes: 8. the voltage on any input or i/o pin cannot exceed the power pin during power-up 9. minimum voltage equals ? 2.0v for pulse duration less than 20 ns. 10. all voltage referenced to ground. 11. overshoot: v ih (ac) < v dd +1.5v for t < t clk /2, power-up: v ih < 2.6v and v dd < 2.4v and v ddq < 1.4v for t < 200 ns. 12. i sb condition: v ref = v dd . all reset pins are high (v dd ). all a in s are low (0v). cs is high (v dd ). en is low (0v). 13. all input pin voltage levels cannot stay between v ih (dc) and v il (dc) in the idle mode. 14. both clocks switching at maximum speeds, data switching at half the clock frequency. v ih (ac) = v ref + 0.2v v il (ac) = v ref - 0.2v v ih (dc) v il (dc) v ref
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 18 of 30 ac test loads and waveforms [15] notes: 15. unless otherwise noted, test conditions assume signal transition time of 2 v/ns, timing reference levels of 0.75v, v ref = 0.75v, rq = 250 ?, v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (b) of ac test loads. ac specifications (a 50 ? load terminated into 0.75v is used with v ddq ) parameter description cy7c480xv25 unit min. max. f max max. frequency 200 mhz t cyc clock cycle time 5 ns t sd input data set-up time 1.0 ns t hd input data hold time 0.6 ns t a access time 3.8 ns [15] (a) test loads (b) test loads v ref (v ddq )/2 output device under test z o = 50 ? r l = 50 ? v th = (v ddq )/2 r l = 50 ? v ref (v ddq )/2 output device under test v th = (v ddq )/2 5 pf all input pulses 0.75v 1.25v 0.25v 10% 90% t r t f 90% 10% t r 0.5 ns, t f 0.5 ns
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 19 of 30 timing parameters parameter description 7c480xv25- 200 7c480xv25- 166 unit min. max. min. max. f s clock frequency, clka or clkb 200 166 mhz t clk clock cycle time, clka or clkb 5 6 ns t clkh pulse duration, clka or clkb high 2.5 3 ns t clkl pulse duration, clka or clkb low 2.5 3 ns t ds data set-up time, a 79 ? 0 before clka 1.0 1.5 ns t ens enable set-up time, csa or ena before clka ; csb or enb before clkb 1.0 1.5 ns t fss set-up time, fs0 and fs1 before mr high 2 2.5 ns t bes set-up time, be/fwft before mr high 3 4 ns t spms set-up time, spm before mr high 2 2.5 ns t rsts set-up time, mr or pr or rt before clk 2.5 3 ns t sds set-up time, fs0/sd before clka 1.0 1.5 ns t sens set-up time, fs1/sen before clka 1.0 1.5 ns t fws set-up time, fwft before clka 1.0 1.5 ns t dh data hold time, a 79 ? 0 after clka 0.6 0.6 ns t enh enable hold time, csa or ena after clka ; csb or enb after clkb 0.6 0.6 ns t fsh hold time, fs0 and fs1 after mr high 2 2.5 ns t beh hold time, be/fwft after mr high 2 2.5 ns t spmh hold time, spm after mr high 2 2.5 ns t rsth hold time, mr or pr or rt after clk 2.5 3 ns t sdh hold time, fs0/sd after clka 0.6 0.6 ns t senh hold time, fs1/sen after clka 0.6 0.6 ns t sph hold time, fs1/sen high after mr high 2 2.5 ns t skew1 skew time between clka and clkb for ef /or and ff /ir 4.5 6.5 ns t skew2 skew time between clka and clkb for ae and af 4.5 6.5 ns t a access time, clkb to b 79 ? 0 3.8 4.0 ns t wff propagation delay time, clka to ff /ir 3.8 4.0 ns t ref propagation delay time, clkb to ef /or 3.8 4.0 ns t pa e propagation delay time, clkb to ae 3.8 4.0 ns t pa f propagation delay time, clka to af 3.8 4.0 ns t rsf propagation delay time, mr or pr low to ae low, af high,ff / ir low and ef / or low 7 7 ns t en enable time, csb low or oe low to b 79 ? 0 active 4.8 4.8 ns t dis disable time, csb high or oe high to b 79 ? 0 at high impedance 4.6 4.6 ns
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 20 of 30 switching waveforms notes: 16. pr must be high during master reset. 17. mr and pr must be low for at least four clock edges (referenced to the slowest clock). 18. t rsts and t rsth are referenced to the slowest clock. 19. t wff is referenced to clka. 20. mr must be high during partial reset. master reset loading x and y with a preset value of eight clk mr be/fwft rt /spm fs1/sen , fs0/sd ff /ir ef /or ae af [16, 17, 18, 19] t rsts t rsth t spms t spmh t bes t beh t fss t fsh t fws t wff t rsf t rsf t rsf t rsf 1234 partial reset (cy standard and fwft modes) clk pr [17, 18, 19, 20] t rsts t rsth ff /ir ef /or ae af t wff t rsf t rsf t rsf t rsf 1234
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 21 of 30 notes: 21. csa = low. it is not necessary to program offset register on consecutive clock cycles. 22. it is not necessary to program offset register bits on consecutive clock cycles. fifo write attempts are ignored until ff /ir is set high. 23. programmable offsets are written serially to the sd input in the order af offset (y) then ae offset (x). switching waveforms (continued) parallel programming of the almost-full flag and almost-empty flag offset values after reset (cypress standard and fwft modes) t wff t fss t ds t spms t spmh t fsh t ens t enh t dh af offset (y) first word into fifo clka mr rt /spm fs1/sen , fs0/sd ff/ ir ena a 0-79 [21] ae offset (x) y x w1 t ens t ens t enh t enh serial programming of the almost-full flag and almost-empty flag offset values (cypress standard and fwft modes) t fss t sph t sens t senh t senh t sens t sdh t sds t sdh t sds t wff af offset (y) msb t spms t spmh clka mr rt /spm ff/ ir fs1/sen fs0/sd ae offset (x) lsb t fss t fsh [22] [23] ae af a 0-79 w1 low t paf
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 22 of 30 note: 24. unused bits b 40 ? 79 are zeroes for word-size reads. switching waveforms (continued) or t clkh t clkl t ens t dis t ens t enh t clk t dis t enh t ens t enh t a t a t a t a t en t en w1 w2 w1 w2 w3 previous data no operation clkb ef /or csb enb b 0 ? 79 (standard mode) b 0 ? 79 (fwft mode) port b long-word read cycle timing for fifo (cypress standard and fwft modes) oe high or t dis t ens t enh t a t a t a t a t en t en t dis previous data read 1 read 1 read 2 read 2 read 3 no operation clkb ef /or csb enb b 0 ? 39 (standard mode) b 0 ? 39 (fwft mode) port b word read cycle timing for fifo (cypress standard and fwft modes) oe [24] high
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 23 of 30 notes: 25. unused bits b 20 ? 79 are zeroes for short word-size reads. 26. unused bits b 10 ? 79 are zeroes for byte-size reads. switching waveforms (continued) or t dis t ens t enh t a t a t a t a t en t en t dis t a t a t a t a previous data read 1 read 1 read 2 read 2 read 3 read 3 read 4 read 4 read 5 no operation high clkb ef /or csb enb b 0 ? 19 (standard mode) b 0 ? 19 (fwft mode) port b short word read cycle timing for fifo (cypress standard and fwft modes) oe [25] or t dis t ens t enh t a t a t a t a t en t en t dis t a t a t a t a previous data read 1 read 1 read 2 read 2 read 3 read 3 read 4 read 4 read 5 no operation high clkb ef /or csb enb b 0 ? 9 (standard mode) b 0 ? 9 (fwft mode) port b byte read cycle timing for fifo (cypress standard and fwft modes) [26] oe
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 24 of 30 notes: 27. if port b size is word, short word, or byte, ef is set low by the last word, short word, or byte read from the fifo, respectively. 28. t skew1 (7 ns minimum) is the time between a rising clka edge and a rising clkb edge for or flag to transition high. if the time betwe en these two edges is less than t skew1 , the transition of or high may occur one clkb cycle later than shown. clka and clkb above are assumed to run at 200mhz (5 ns cycle time), which results in or flag being updated after the fourth clkb edge. if the clock cycles are more than 7 ns, or flag may get updated after the third clock edge, depending on when the clock edges occur. in general, or flag update cycle = (t skew1 ) + (2 clock cycle) + (t ref ). switching waveforms (continued) t clkh t clkl t ens t clk t enh t a t ds w1 low t dh high fifo empty low old data in fifo output register w1 t ens t ref t ref t clkh t clkl t clk t skew1 [28] clka csa ena ff /ir a 0 ? 79 clkb ef /or csb enb b 0-79 or flag timing and first data word fall through when fifo is empty (fwft mode) low oe [27] t enh
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 25 of 30 notes: 29. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for ef to transition high. if the time between these two edges is less than t skew1 , the transition of ef high may occur one clkb cycle later than shown. clka and clkb above are assumed to run at 200 mhz (5 ns cycle time), which results in ef flag being updated after the third clkb edge. if the clock cycles are more than 7 ns, ef flag may get updated after the second clock edge, depending on when the clock edges occur. in general, ef flag update cycle = (t skew1 ) + (1 clock cycle) + (t ref ). switching waveforms (continued) t clkh t clkl t ens t enh t a t ds w1 low t dh high fifo empty low w1 t ens t enh t ref t ref t clk t skew1 [29] clka csa ena ff /ir a 0 ? 79 clkb ef /or csb enb b 0 ? 79 ef flag timing and first data read fall through when fifo is empty (cypress standard mode) [27] low oe
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 26 of 30 notes: 30. if port b size is word, short word, or byte, t skew1 is referenced to the rising clkb edge that reads the last word, short word, or byte write of the long-word, respectively. 31. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ff /ir to transition high. if the time between the rising clkb edge and rising clka edge is less than t skew1 , the transition of ff /ir high may occur one clka cycle later than shown. clka and clkb above are assumed to run at 200 mhz (5 ns cycle time), which results in ff /ir flag being updated after the third clka edge. if the clock cycles are more than 7 ns, ff /ir flag may get updated after the second clock edge, depending on when the clock edges occur. in general, ff /ir flag update cycle = (t skew1 ) + (1 clock cycle) + (t wff ). switching waveforms (continued) t clkh t clkl t ens t enh t a low high fifo full low t ens t enh t wff t wff t clkh t clkl t clk t clk t skew1 [31] t dh t ds previous word in fifo output register next word from fifo clkb csb enb ef /or b 0 ? 79 clka ff /ir csa ena a 0 ? 79 ff /ir flag timing and first available write when fifo is full (cypress standard and fwft mode) [30]
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 27 of 30 notes: 32. fifo write (csa = low) on port a, fifo read (csb = low) on port b. data in the fifo output register has been read from the fifo. 33. d = maximum fifo depth = 4k for the CY7C4804V25, 16k for the cy7c4806v25, and 64k for the cy7c4808v25. 34. if port b size is word, short word or byte, t skew2 is referenced to the rising clkb edge that writes the last word, short word or byte of the long word, respectively. 35. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for af to transition high in the next clka cycle. if the time between these two edges is less than t skew2 , af may transition high one clkb cycle later than shown. clka and clkb above are assumed to run at 200 mhz (5 ns cycle time), which results in af flag being updated after the third clka edge. if the clock cycles are more than 7 ns, af flag may get updated after the second clock edge, depending on when the clock edges occur. in general, af flag update cycle = (t skew2 ) + (1 clock cycle) + (t paf ). 36. fifo write (csa = low) on port a, fifo read (csb = low) on port b. data in the fifo output register has been read from the fifo. 37. if port b size is word, short word, or byte, ae is set low by the last word, short word, or byte read from fifo, respectively. 38. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for ae to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , ae may transition high one clkb cycle later than shown. clka and clkb above are assumed to run at 200 mhz (5 ns cycle time), which results in ae flag being updated after the third clkb edge. if the clock cycles are more than 7 ns, ae flag may get updated after the second clock edge, depending on when the clock edges occur. in general, ae flag update cycle = (t skew2 ) + (1 clock cycle) + (t pae ). switching waveforms (continued) timing for af when fifo is almost full (cypress standard and fwft modes) t skew2 [35] clka ena af clkb enb [32, 33, 34] t paf t enh t ens t paf t ens t enh [d ? (y + 1)] words in fifo (d ? y) words in fifo [d ? (y + 2)] words in fifo t enh t ens t ens clka ena clkb ae enb timing for ae when fifo is almost empty (cypress standard and fwft modes) t pae t pae t enh t ens t ens t enh x word in fifo (x + 1) words in fifo [36, 37] t enh t ens t ens t enh (x + 1) word in fifo x word in fifo (x + 2 ) word in fifo t skew2 [38]
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 28 of 30 notes: 39. clocks are free-running in this case. 40. rt must be low for at least eight clock edges (referenced to the slowest clock). 41. t rsts and t rsth are referenced to the slowest clock. 42. ff goes back high at the second clka edge after rt goes high. 43. af goes back high at the first clka edge after rt goes high. 44. ae goes back high at the first clkb edge after rt goes high. 45. t paf and t wff are referenced to clka. 46. t ref , t ens , and t pae are referenced to clkb. switching waveforms (continued) fifo retransmit timing enb rt ef [39, 40, 41, 42, 43, 44, 45, 46] clkb t ref t ref (std) (std)dd (fwft) (cy) or 12345678 12345678910 (cy) enb (fwft) t ens t rsts t rsth t ens e ae clka ff af clk t paf t wff t pae
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 29 of 30 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. all product and company names mentioned in this document are the trademarks of their respective holders. package diagram 288-ball grid array (1.0 pitch, 19 19 mm) bb288 51-85129
cy7c4808v25 cy7c4806v25 CY7C4804V25 preliminary document #: 38-06028 rev. *b page 30 of 30 document title: cy7c4808v25, cy7c4806v25, CY7C4804V25 2.5v 4k/16k/64k 80 unidirectional synchronous fifo with bus matching document number: 38-06028 rev. ecn no. issue date orig. of change description of change ** 109959 10/21/01 szv change from spec number: 38-00874 to 38-06028 *a 111337 02/07/01 jfu 1. updated access time values 2. updated i sb conditions 3. updated idle mode conditions 4. updated operating current values 5. revised master and partial reset timing diagrams 6. revised fifo retransmit timing diagram *b 122280 12/26/02 rbi power up requirements added to maximum ratings information

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